[PATCH] D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
alex-t added reviewers: rampitec, foad.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl, arsenm.
alex-t requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

This change includes tablegen patterns that were missed by https://reviews.llvm.org/D110950 and https://reviews.llvm.org/D76230


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119302

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
  llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
  llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll

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