[PATCH] D119006: [AMDGPU] SILoadStoreOptimizer: avoid unbounded register pressure increases

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D119006#3301526 <https://reviews.llvm.org/D119006#3301526>, @piotr wrote:

> So that indicates an improvement in the average vgpr count.

Yes.

> Btw, does the patch result in a noticeably smaller number of merges on average?

No, to my surprise there was absolutely no difference in the amount of merging in any of the 10,000 shaders. I checked by diffing the instruction mix for each shader. The only differences were in VALU and SALU instructions.



================
Comment at: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:604-605
+    return false;
+  // TODO: Use LaneMasks for virtregs to allow non-conflicting subreg uses/defs.
+  // FIXME: Use RegUnits for physreg operands to detect partial overlaps.
+  for (const auto &BOp : B.operands()) {
----------------
arsenm wrote:
> Generally those don't exist at this point outside of copies
What don't? Subregs or partial physreg overlaps or both?


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