[PATCH] D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:601
+  } else {
+    Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
   }
----------------
rampitec wrote:
> It misses error reporting and setRegUsed call.
Ping.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:603
     }
+  } else if (ST.hasMAIInsts() & MFI->usesAGPRs(MF)) {
+    // In order to guarantee copying between AGPRs, we need a scratch VGPR
----------------
rampitec wrote:
> Still "&& !ST.hasGFX90AInsts()".
> Use logical and.
Still need !ST.hasGFX90AInsts().


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118415/new/

https://reviews.llvm.org/D118415