[PATCH] D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908

Thu Feb 3 11:57:11 PST 2022

arsenm added a comment.

In D118415#3294534 <https://reviews.llvm.org/D118415#3294534>, @rampitec wrote:

> In D118415#3294512 <https://reviews.llvm.org/D118415#3294512>, @arsenm wrote:
>
>> In D118415#3278088 <https://reviews.llvm.org/D118415#3278088>, @rampitec wrote:
>>
>>> On the second thought, scavengeRegister will spill if nothing is available. Isn't that sufficient?
>>
>> There's no emergency scavenging slot set up for the scavenger here. It's also insane and quadratic to set up the scavenger for every copy we need to process. The assumption is also that copies between 2 registers should always be fast, which isn't the case if there could be a spill here
>
> It's not every copy, it is an emergency situation though? Reserving a register in the middle of the register file is really a last resort thing.

The fact that it can happen from just a copy is an issue. Combined with the issue in D115401 <https://reviews.llvm.org/D115401>, I don't see a perfectly reliable system without reserving a register. If we wanted to scavenge here, we would need to have the pass maintain the liveness instead of repeating it every iteration which adds a lot more expense too.

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