[PATCH] D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D118415#3294512 <https://reviews.llvm.org/D118415#3294512>, @arsenm wrote:

> In D118415#3278088 <https://reviews.llvm.org/D118415#3278088>, @rampitec wrote:
>
>> On the second thought, scavengeRegister will spill if nothing is available. Isn't that sufficient?
>
> There's no emergency scavenging slot set up for the scavenger here. It's also insane and quadratic to set up the scavenger for every copy we need to process. The assumption is also that copies between 2 registers should always be fast, which isn't the case if there could be a spill here

It's not every copy, it is an emergency situation though? Reserving a register in the middle of the register file is really a last resort thing.


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