[PATCH] D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D118415#3278088 <https://reviews.llvm.org/D118415#3278088>, @rampitec wrote:

> On the second thought, scavengeRegister will spill if nothing is available. Isn't that sufficient?

There's no emergency scavenging slot set up for the scavenger here. It's also insane and quadratic to set up the scavenger for every copy we need to process. The assumption is also that copies between 2 registers should always be fast, which isn't the case if there could be a spill here


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