[PATCH] D118394: [AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP

Tue Feb 1 06:36:30 PST 2022

DavidTruby added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/vector-fcopysign.ll:303
+; NOFP16-NEXT:    bsl.16b v1, v2, v4
+; NOFP16-NEXT:    fcvt h1, s1
 ; NOFP16-NEXT:    mov.h v0[3], v1[0]
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efriedma wrote:
> It looks like the generated code here got worse; is there something wrong with the way we lower AArch64ISD::BSP?
This looks like an oddity of register allocation to me. I'm not sure why the bsl instruction doesn't just use v3, in which case the extra mov wouldn't be necessary. By the time we get to AArch64ISD::BSP lowering register allocation has already happened though. I'm not sure what the solution to that is.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118394/new/

https://reviews.llvm.org/D118394