[PATCH] D117689: [AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fp-vselect.ll:4-12
+define <vscale x 8 x half> @vselect_fmul_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: vselect_fmul_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmul z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+    %mul = fmul <vscale x 8 x half> %a, %b
+    %x = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %mul
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paulwalker-arm wrote:
> Are these tests correct? To me it looks like you've got the true and false operands the wrong way round.  This IR is effectively saying "when the predicate it true return op1 else return op1 * op2".
> 
> The fact the generate code is what we're after suggests the same mistake exists for the new isel patterns.
> 
The tests aren't correct, I missed the fact that `fcmeq` in the sqrt example is creating a predicate of 1s. Is it possible to reverse the operands for specific patterns in the PatFrags list? If not I'll have to split up parts of the logic introduced in this patch


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  https://reviews.llvm.org/D117689/new/

https://reviews.llvm.org/D117689