[PATCH] D117689: [AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

I'd focus on one thing at a time.  This patch enables the isel required for the way merged arithmetic is modelled by the DAG.  Once that is complete you can see what's needed to improve the reciprocal code.  For that follow-on work I'm guessing you'll need a DAG combine for the select that inverts the comparison for the cases where this'll be beneficial.


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https://reviews.llvm.org/D117689