[PATCH] D117689: [AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:168
 def SDT_AArch64Arith : SDTypeProfile<1, 3, [
-  SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
-  SDTCVecEltisVT<1,i1>, SDTCisSameAs<0,2>, SDTCisSameAs<2,3>
+  SDTCVecEltisVT<1,i1>, SDTCisSameAs<0,2>, SDTCisSameAs<2,3>, SDTCisSameNumEltsAs<0,1>
 ]>;
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I cannot say if it really matters (given `SDTCisSameNumEltsAs<0,1>` implies 0 must be a vector) but I'd be inclined to keep `SDTCisVec<0>`. 


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Comment at: llvm/test/CodeGen/AArch64/sve-fp-vselect.ll:4-12
+define <vscale x 8 x half> @vselect_fmul_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: vselect_fmul_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmul z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+    %mul = fmul <vscale x 8 x half> %a, %b
+    %x = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %mul
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Are these tests correct? To me it looks like you've got the true and false operands the wrong way round.  This IR is effectively saying "when the predicate it true return op1 else return op1 * op2".

The fact the generate code is what we're after suggests the same mistake exists for the new isel patterns.



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  https://reviews.llvm.org/D117689/new/

https://reviews.llvm.org/D117689