[PATCH] D115691: [PowerPC] Update P10 vector insert patterns to use refactored load/stores, and update handling of v4f32 vector insert.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM other than the change to the comment.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10757-10762
+    // A f32 load feeding into a v4f32 insert_vector_elt is handled in this way
+    // because on P10, it allows this specific insert_vector_elt load pattern to
+    // utilize the refactored load and store infrastructure in order to exploit
+    // prefixed loads.
+    // Additionally, on Power9, this enables utilizing direct moves (which are
+    // cheaper than the alternative sequence).
----------------
Please note that your description re. Power10 is temporal in nature. The "refactored load and store infrastructure..." is newly refactored now. In the future, it will just be how we select loads and stores (i.e. code has no memory of how it looked before). I think it would suffice to add something like this as a comment:
```
// On targets with inexpensive direct moves (Power9 and up), a
// (insert_vector_elt v4f32:$vec, (f32 load)) is always better as an
// integer load since a single precision load will involve conversion
// to double precision on the load followed by another conversion
// to single precision.
```


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https://reviews.llvm.org/D115691