[PATCH] D115691: [PowerPC] Update P10 vector insert patterns to use refactored load/stores, and update handling of v4f32 vector insert.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2817
             (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddr:$rA)), i64:$rB)),
-            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (LWZ memri:$rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), i64:$rB)),
+  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load PDForm:$rA)), i64:$rB)),
             (VINSWRX $vDi, InsertEltShift.Sub32Left2, (PLWZ memri34:$rA))>;
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I think that you should be able to remove all of the patterns for load+insert with `f32` since they will not make it to instruction selection (i.e. they're all being converted to `i32`).


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  https://reviews.llvm.org/D115691/new/

https://reviews.llvm.org/D115691