[PATCH] D118054: [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node.

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. LGTM



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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:337
 def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>;
+def SDT_AArch64PFalse : SDTypeProfile<1, 0, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>]>;
+def AArch64pfalse : SDNode<"AArch64ISD::PFALSE", SDT_AArch64PFalse>;
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sdesmalen wrote:
> dmgreen wrote:
> > Does SDTCVecEltisVT imply SDTCisVec?
> Not sure, but when I add a pattern with `i1` type, tblgen seems to go into an infinite loop.
I think it should be fine without, from the use of SDTCVecEltisVT in other backends (and, you know, we only create AArch64ISD::PFALSE for vectors anyway..)


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  https://reviews.llvm.org/D118054/new/

https://reviews.llvm.org/D118054