[PATCH] D118054: [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node.

[Sander de Smalen via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd58757e522a4: [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node. (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118054/new/

https://reviews.llvm.org/D118054

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-pfalse-machine-cse.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D118054.403556.patch
Type: text/x-patch
Size: 4169 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220127/dfa05d68/attachment.bin>