[PATCH] D118054: [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:2198
     MAKE_CASE(AArch64ISD::PTEST)
     MAKE_CASE(AArch64ISD::PTRUE)
     MAKE_CASE(AArch64ISD::LD1_MERGE_ZERO)
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dmgreen wrote:
> Add a case here too, so it gets printed nicely in debug output.
Good spot, cheers!


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:337
 def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>;
+def SDT_AArch64PFalse : SDTypeProfile<1, 0, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>]>;
+def AArch64pfalse : SDNode<"AArch64ISD::PFALSE", SDT_AArch64PFalse>;
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dmgreen wrote:
> Does SDTCVecEltisVT imply SDTCisVec?
Not sure, but when I add a pattern with `i1` type, tblgen seems to go into an infinite loop.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D118054/new/

https://reviews.llvm.org/D118054