[PATCH] D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead updated this revision to Diff 401858.
pcwang-thead added a comment.

- Rebase.
- Revert to the original version.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117741/new/

https://reviews.llvm.org/D117741

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/add-before-shl.ll
  llvm/test/CodeGen/RISCV/addcarry.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
  llvm/test/CodeGen/RISCV/double-arith-strict.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
  llvm/test/CodeGen/RISCV/double-fcmp.ll
  llvm/test/CodeGen/RISCV/float-arith-strict.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fp128.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-intrinsics.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/remat.ll
  llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbt.ll
  llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vpstore.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/sadd_sat.ll
  llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll
  llvm/test/CodeGen/RISCV/shadowcallstack.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/ssub_sat.ll
  llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
  llvm/test/CodeGen/RISCV/stack-store-check.ll
  llvm/test/CodeGen/RISCV/tail-calls.ll
  llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
  llvm/test/CodeGen/RISCV/xaluo.ll