[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan updated this revision to Diff 401482.
jacquesguan added a comment.

Add patterns for riscv_zext_vl and riscv_sext_vl


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117643/new/

https://reviews.llvm.org/D117643

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117643.401482.patch
Type: text/x-patch
Size: 39318 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220120/4710f2ac/attachment.bin>