[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D117643#3255008 <https://reviews.llvm.org/D117643#3255008>, @craig.topper wrote:

> In D117643#3254919 <https://reviews.llvm.org/D117643#3254919>, @frasercrmck wrote:
>
>> It'd be nice to see this work for fixed vectors too as I'm concerned we're starting to diverge in support between this and other recent patches, but I suppose we'd need extra patterns for the `riscv_sext_vl` and `riscv_zext_vl`, right?
>
> Widening for fixed vector MUL is done with a DAG combine. It handles the extend being before the splat instead of after which is going to be the common case for autovectorized code if the splat is loop invariant. It also handles reducing i8->i32 extends to i8->i16 followed by a widening MUL. These are both hard to do in an isel pattern.

I added patterns for riscv_sext_vl` and `riscv_zext_vl`, it does take effect, but in some case, I think also need to support the pattern matching `riscv_add_vl` to widen instruction.


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