[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:651
+    defvar wti_m1 = !cast<VTypeInfo>("VI"#wti.SEW#"M1");
+    def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+                                 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
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frasercrmck wrote:
> The "true mask" case isn't tested by this patch.
I think this pattern with `true_mask` means unmasked, and the cases in `llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll` already test this?



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  https://reviews.llvm.org/D117643/new/

https://reviews.llvm.org/D117643