[PATCH] D117406: [DAGCombiner] Adjust some checks in DAGCombiner::reduceLoadWidth

Tue Jan 18 02:27:24 PST 2022

bjope added inline comments.

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Comment at: llvm/test/CodeGen/X86/combine-srl-load.ll:7
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzwl 1(%rdi), %eax
+; CHECK-NEXT:    retq
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bjope wrote:
> I've assumed that DAGCombiner::isLegalNarrowLdSt would have bailed out if this would result in a unaligned memory access for the target (it does use TLI.allowsMemoryAccess).
> 
> Had perhaps been nice with a test case for some target where this would matter. Any suggestions?
Well, I've verified it by using riscv64 as a target. Not sure if I need to add a test case for that.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117406/new/

https://reviews.llvm.org/D117406