[PATCH] D117406: [DAGCombiner] Adjust some checks in DAGCombiner::reduceLoadWidth

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added inline comments.


================
Comment at: llvm/test/CodeGen/X86/combine-srl-load.ll:7
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzwl 1(%rdi), %eax
+; CHECK-NEXT:    retq
----------------
I've assumed that DAGCombiner::isLegalNarrowLdSt would have bailed out if this would result in a unaligned memory access for the target (it does use TLI.allowsMemoryAccess).

Had perhaps been nice with a test case for some target where this would matter. Any suggestions?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117406/new/

https://reviews.llvm.org/D117406