[PATCH] D117406: [DAGCombiner] Adjust some checks in DAGCombiner::reduceLoadWidth

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12220
+    // Avoid reading outside the memory accessed by the original load (could
+    // happend if we only adjust the load base pointer by ShAmt). Instead we try
+    // to narrow the load even further. The typical scenario here is:
----------------
happend -> happen


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12226-12227
+      assert(ExtType != ISD::SEXTLOAD && "Don't replace sextload by zextload.");
+      ExtType = ISD::ZEXTLOAD;
+      ExtVT = EVT::getIntegerVT(*DAG.getContext(), MemoryWidth - ShAmt);
       return SDValue();
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Why set these variables if we are exiting the function? Can we specify in the comment which function does the narrowing of the load for this pattern?


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Comment at: llvm/test/CodeGen/X86/combine-srl-load.ll:4
+
+define i16 @load_srl_combine(i32* %arg) {
+; CHECK-LABEL: load_srl_combine:
----------------
It would better to pre-commit this test with the baseline CHECKs. I don't think there's a specific test file for x86 used for verifying this type of fold, but "shift-folding.ll" has a test that looks similar, so you could add it to that file.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117406/new/

https://reviews.llvm.org/D117406