[PATCH] D117538: [RISCV] Add instruction schedule for Zbc extension and Zbs extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:369
+def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">,
+            Sched<[WriteSingleBitImm, ReadSingleBitImm, ReadSingleBitImm]>;
+def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">,
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There should only be one ReadSingleBitImm. There's only one source register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117538/new/

https://reviews.llvm.org/D117538