[PATCH] D117538: [RISCV] Add instruction schedule for Zbc extension and Zbs extension

[WangLian via Phabricator via llvm-commits]

Jimerlife updated this revision to Diff 400729.
Jimerlife added a comment.

update BCLRI/BSETI/BINVI/BEXTI schedule operand


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117538/new/

https://reviews.llvm.org/D117538

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleB.td

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