[PATCH] D117538: [RISCV] Add instruction schedule for Zbc extension and Zbs extension

[WangLian via Phabricator via llvm-commits]

Jimerlife created this revision.
Jimerlife added reviewers: craig.topper, benshi001, asb, jrtc27.
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Zbc extension:
CLMUL/CLMULR/CLMULH are grouped together, defined one schedule class.

Zbs extension:
BCLR/BSET/BINV/BEXT are grouped together, defined one schedule class.
BCLRI/BSETI/BINVI/BEXTI are grouped together, defined one schedule class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117538

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleB.td

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