[PATCH] D117385: [RISCV] Add patterns for vector widening integer multiply

Mon Jan 17 11:09:43 PST 2022

craig.topper added a comment.

In D117385#3247401 <https://reviews.llvm.org/D117385#3247401>, @jacquesguan wrote:

> In D117385#3246290 <https://reviews.llvm.org/D117385#3246290>, @craig.topper wrote:
>
>> What about vwmulsu?
>>
>> I am curious what we should do for something like (nxvXi32 (mul (sext (nxvXi8 X)), (sext (nxvXi8 Y)).  Should we leave the sexts alone or should be shrink them to (nxvXi16 (sext (nxvXi8 X)) and use a widening multiply to do the rest of the extend?
>
> I think that maybe `(nxvXi32 (mul (sext (nxvXi8 X)), (sext (nxvXi8 Y)) -> (nxvXi32 sext (mul (nxvXi16 (sext (nxvXi8 X))), (nxvXi16 (sext (nxvXi8 Y)))))` is better? In this way, we could use less width vector to calaculate, it could be faster?

That's a good point. I guess my question better applies to the case where one type is 16 bits, the other is 8 bits and the result is 32 bits.

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https://reviews.llvm.org/D117385