[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4127
+        }
+        // We will use vmv.x.s to extract the elment to GPR, and if eew is less
+        // than XLEN, the value will be signed extend.
----------------
elment -> element


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4131
+        // GPR bit    | XLEN -1 |--------------| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+        // mask index |    7    |--------------| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+        // So if we want to extract the 7th element, we should set extract bit
----------------
Sign extend means that bit 7 and above all have the same value. So why can't we just check bit 7?


Repository:
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  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389