[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll:68
+; RV32-NEXT:    li a0, 7
+; RV32-NEXT:    sub a0, a0, a1
+; RV32-NEXT:    vmv.x.s a1, v8
----------------
craig.topper wrote:
> jacquesguan wrote:
> > craig.topper wrote:
> > > I don't think I understand what this subtract is doing.
> > We will use vmv.x.s to extract the elment to GPR, and if eew is less than XLEN, the value will be signed extend. For example, for 8 x i1 mask vector, we will have:
> > ```
> >         GPR bit    | XLEN -1 |--------------| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
> >         mask index |    0    |--------------| 1 | 2 | 3 | 4 | 5 | 6 | 7 |
> > ```
> > So if we want to extract the 0th element, we should set extract bit index to XLEN - 1, and otherwise the index = element width - 1 - mask index.
> Why would the mask bits be in reversed order?
It is my mistake, I thought things in wrong way. Here should not be in reversed order. I fixed it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389