[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4112
+        } else {
+          WideEleVT = XLenVT;
+          WidenVecLen = Nums / XLenVT.getScalarSizeInBits();
----------------
jacquesguan wrote:
> craig.topper wrote:
> > This won't work with Zve32 on RV64. A vector XLen elements wouldn't be legal.
> I add `MaxEEW` to get the right largest vector element width that we could have on current target, but we do not support `Zve` extension now, so I just set it to 64 and add a `TODO` to  remind changing it after having `Zve`.
You don't need Zve to test this. Before Zve was added to the spec we added a command line option "-riscv-v-fixed-length-vector-elen-max" to clip the ELEN.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389