[PATCH] D117454: [RISCV] Add patterns for vector narrowing integer right shift instructions

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:609
+      (vti.Vti.Vector 
+        (riscv_trunc_vector_vl
+          (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
----------------
jacquesguan wrote:
> Because here we always have truncate from `SEW*2` to `SEW`, could we directly use trunc here and move these classes and patterns to `RISCVInstrInfoVSDPatterns.td`? In this way, maybe no need to use `(riscv_vmset_vl (XLenVT -1))` for mask and `(XLenVT -1)` for vl.
I have tried to use `trunc` and found out we can't do this. The reason is that the RISCV backend only support one stage of truncate. So the compiler will first legalize it to `RISCVISD::TRUNCATE_VECTOR_VL` and split it into step(s) (e.g. if doing `i64 -> i16`, it will turnt into 2 instruction)

Here are the llc debug message to show you the "legalization" from `trunc` to `RISCVISD::TRUNCATE_VECTOR_VL`:

```
Type-legalized selection DAG: %bb.0 'vnsrl_wv_nxv1i32:'
SelectionDAG has 11 nodes:
  t0: ch = EntryToken
        t2: nxv1i64,ch = CopyFromReg t0, Register:nxv1i64 %0
          t4: nxv1i32,ch = CopyFromReg t0, Register:nxv1i32 %1
        t6: nxv1i64 = sign_extend t4
      t7: nxv1i64 = srl t2, t6
    t8: nxv1i32 = truncate t7
  t11: ch,glue = CopyToReg t0, Register:nxv1i32 $v8, t8
  t12: ch = RISCVISD::RET_FLAG t11, Register:nxv1i32 $v8, t11:1



Legalizing vector op: t6: nxv1i64 = sign_extend t4
Trying custom legalization

Legalizing vector op: t7: nxv1i64 = srl t2, t6
Legal node: nothing to do

Legalizing vector op: t8: nxv1i32 = truncate t7
Trying custom legalization
Creating constant: t13: i32 = TargetConstant<-1>
Creating new node: t14: nxv1i1 = RISCVISD::VMSET_VL TargetConstant:i32<-1>
Creating new node: t15: nxv1i32 = RISCVISD::TRUNCATE_VECTOR_VL t7, t14, TargetConstant:i32<-1>
Vector-legalized selection DAG: %bb.0 'vnsrl_wv_nxv1i32:'
SelectionDAG has 13 nodes:
  t0: ch = EntryToken
        t2: nxv1i64,ch = CopyFromReg t0, Register:nxv1i64 %0
          t4: nxv1i32,ch = CopyFromReg t0, Register:nxv1i32 %1
        t6: nxv1i64 = sign_extend t4
      t7: nxv1i64 = srl t2, t6
      t14: nxv1i1 = RISCVISD::VMSET_VL TargetConstant:i32<-1>
    t15: nxv1i32 = RISCVISD::TRUNCATE_VECTOR_VL t7, t14, TargetConstant:i32<-1>
  t11: ch,glue = CopyToReg t0, Register:nxv1i32 $v8, t15
  t12: ch = RISCVISD::RET_FLAG t11, Register:nxv1i32 $v8, t11:1
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117454/new/

https://reviews.llvm.org/D117454