[PATCH] D117454: [RISCV] Add patterns for vector narrowing integer right shift instructions

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:609
+      (vti.Vti.Vector 
+        (riscv_trunc_vector_vl
+          (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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Because here we always have truncate from `SEW*2` to `SEW`, could we directly use trunc here and move these classes and patterns to `RISCVInstrInfoVSDPatterns.td`? In this way, maybe no need to use `(riscv_vmset_vl (XLenVT -1))` for mask and `(XLenVT -1)` for vl.


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  https://reviews.llvm.org/D117454/new/

https://reviews.llvm.org/D117454