[PATCH] D117454: [RISCV] Add patterns for vector narrowing integer right shift instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:612
+              (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
+          (riscv_vmset_vl (XLenVT -1)),
+          (XLenVT -1))),
----------------
`(XlenVT -1)` -> `VLMax`


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:613
+          (riscv_vmset_vl (XLenVT -1)),
+          (XLenVT -1))),
+      (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
----------------
`(XlenVT -1)` -> `VLMax`


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:627
+              (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
+          (riscv_vmset_vl (XLenVT -1)),
+          (XLenVT -1))),
----------------
Same here


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117454/new/

https://reviews.llvm.org/D117454