[PATCH] D117454: [RISCV] Add patterns for vector narrowing integer right shift instructions

Yueh-Ting Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 17 01:37:45 PST 2022


eopXD added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:611
+          (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+              (vti.Wti.Vector (sext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
+          (riscv_vmset_vl (XLenVT -1)),
----------------
jacquesguan wrote:
> Because only the low lg2(2*SEW) bits of the shift-amount value are used, I think we could also add zero extend here.
Good idea, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117454/new/

https://reviews.llvm.org/D117454



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