[llvm] 1ca7982 - [RISCV] Add CSRs defined in the recently ratified Smstateen extension

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2022-01-15T08:35:47Z
New Revision: 1ca79823e0562be2a065377dda1474b0dc9c9e4d

URL: https://github.com/llvm/llvm-project/commit/1ca79823e0562be2a065377dda1474b0dc9c9e4d
DIFF: https://github.com/llvm/llvm-project/commit/1ca79823e0562be2a065377dda1474b0dc9c9e4d.diff

LOG: [RISCV] Add CSRs defined in the recently ratified Smstateen extension

The "RISC-V State Enable Extension" was ratified at the end of at the
end of last year though hasn't yet been integrated in the main
specification documents (see
<https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions>).

This commit adds the CSRs defined by this extension in
<https://github.com/riscv/riscv-state-enable/releases/download/v0.6.3/Smstateen.pdf>.

Differential Revision: https://reviews.llvm.org/D117310

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSystemOperands.td
    llvm/test/MC/RISCV/hypervisor-csr-names.s
    llvm/test/MC/RISCV/machine-csr-names.s
    llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
    llvm/test/MC/RISCV/rv32-machine-csr-names.s
    llvm/test/MC/RISCV/rv32-only-csr-names.s
    llvm/test/MC/RISCV/supervisor-csr-names.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 2677016dc431..78af112b0291 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -349,3 +349,20 @@ def : SysReg<"vcsr", 0x00F>;
 def : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def SysRegVLENB: SysReg<"vlenb", 0xC22>;
+
+//===----------------------------------------------------------------------===//
+// State Enable Extension (Smstateen)
+//===----------------------------------------------------------------------===//
+
+// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F,
+// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F,
+// and hstateen0h-hstateen3h at 0x61C-0x61F.
+foreach i = 0...3 in {
+  def : SysReg<"sstateen"#i, !add(0x10C, i)>;
+  def : SysReg<"mstateen"#i, !add(0x30C, i)>;
+  let isRV32Only = 1 in
+  def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>;
+  def : SysReg<"hstateen"#i, !add(0x60C, i)>;
+  let isRV32Only = 1 in
+  def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
+}

diff  --git a/llvm/test/MC/RISCV/hypervisor-csr-names.s b/llvm/test/MC/RISCV/hypervisor-csr-names.s
index 07f267d5e4a7..8f76b3d1450d 100644
--- a/llvm/test/MC/RISCV/hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/hypervisor-csr-names.s
@@ -373,3 +373,63 @@ csrrs t2, 0x244, zero
 csrrs t1, vsatp, zero
 # uimm12
 csrrs t2, 0x280, zero
+
+#########################################
+# State Enable Extension (Smstateen)
+#########################################
+
+# hstateen0
+# name
+# CHECK-INST: csrrs t1, hstateen0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x60]
+# CHECK-INST-ALIAS: csrr t1, hstateen0
+# uimm12
+# CHECK-INST: csrrs t2, hstateen0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x60]
+# CHECK-INST-ALIAS: csrr t2, hstateen0
+# name
+csrrs t1, hstateen0, zero
+# uimm12
+csrrs t2, 0x60C, zero
+
+# hstateen1
+# name
+# CHECK-INST: csrrs t1, hstateen1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x60]
+# CHECK-INST-ALIAS: csrr t1, hstateen1
+# uimm12
+# CHECK-INST: csrrs t2, hstateen1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x60]
+# CHECK-INST-ALIAS: csrr t2, hstateen1
+# name
+csrrs t1, hstateen1, zero
+# uimm12
+csrrs t2, 0x60D, zero
+
+# hstateen2
+# name
+# CHECK-INST: csrrs t1, hstateen2, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x60]
+# CHECK-INST-ALIAS: csrr t1, hstateen2
+# uimm12
+# CHECK-INST: csrrs t2, hstateen2, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x60]
+# CHECK-INST-ALIAS: csrr t2, hstateen2
+# name
+csrrs t1, hstateen2, zero
+# uimm12
+csrrs t2, 0x60E, zero
+
+# hstateen3
+# name
+# CHECK-INST: csrrs t1, hstateen3, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x60]
+# CHECK-INST-ALIAS: csrr t1, hstateen3
+# uimm12
+# CHECK-INST: csrrs t2, hstateen3, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x60]
+# CHECK-INST-ALIAS: csrr t2, hstateen3
+# name
+csrrs t1, hstateen3, zero
+# uimm12
+csrrs t2, 0x60F, zero

diff  --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index 603ae28ff188..7e3efce5c5a2 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -2350,3 +2350,63 @@ csrrs t2, 0x33E, zero
 csrrs t1, mhpmevent31, zero
 # uimm12
 csrrs t2, 0x33F, zero
+
+#########################################
+# State Enable Extension (Smstateen)
+#########################################
+
+# mstateen0
+# name
+# CHECK-INST: csrrs t1, mstateen0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x30]
+# CHECK-INST-ALIAS: csrr t1, mstateen0
+# uimm12
+# CHECK-INST: csrrs t2, mstateen0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x30]
+# CHECK-INST-ALIAS: csrr t2, mstateen0
+# name
+csrrs t1, mstateen0, zero
+# uimm12
+csrrs t2, 0x30C, zero
+
+# mstateen1
+# name
+# CHECK-INST: csrrs t1, mstateen1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x30]
+# CHECK-INST-ALIAS: csrr t1, mstateen1
+# uimm12
+# CHECK-INST: csrrs t2, mstateen1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x30]
+# CHECK-INST-ALIAS: csrr t2, mstateen1
+# name
+csrrs t1, mstateen1, zero
+# uimm12
+csrrs t2, 0x30D, zero
+
+# mstateen2
+# name
+# CHECK-INST: csrrs t1, mstateen2, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x30]
+# CHECK-INST-ALIAS: csrr t1, mstateen2
+# uimm12
+# CHECK-INST: csrrs t2, mstateen2, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x30]
+# CHECK-INST-ALIAS: csrr t2, mstateen2
+# name
+csrrs t1, mstateen2, zero
+# uimm12
+csrrs t2, 0x30E, zero
+
+# mstateen3
+# name
+# CHECK-INST: csrrs t1, mstateen3, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x30]
+# CHECK-INST-ALIAS: csrr t1, mstateen3
+# uimm12
+# CHECK-INST: csrrs t2, mstateen3, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x30]
+# CHECK-INST-ALIAS: csrr t2, mstateen3
+# name
+csrrs t1, mstateen3, zero
+# uimm12
+csrrs t2, 0x30F, zero

diff  --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index bc981f99a02b..c84553b578c1 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -39,3 +39,63 @@ csrrs t2, 0x61A, zero
 csrrs t1, htimedeltah, zero
 # uimm12
 csrrs t2, 0x615, zero
+
+#########################################
+# State Enable Extension (Smstateen)
+#########################################
+
+# hstateen0h
+# name
+# CHECK-INST: csrrs t1, hstateen0h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x61]
+# CHECK-INST-ALIAS: csrr t1, hstateen0h
+# uimm12
+# CHECK-INST: csrrs t2, hstateen0h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x61]
+# CHECK-INST-ALIAS: csrr t2, hstateen0h
+# name
+csrrs t1, hstateen0h, zero
+# uimm12
+csrrs t2, 0x61C, zero
+
+# hstateen1h
+# name
+# CHECK-INST: csrrs t1, hstateen1h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x61]
+# CHECK-INST-ALIAS: csrr t1, hstateen1h
+# uimm12
+# CHECK-INST: csrrs t2, hstateen1h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x61]
+# CHECK-INST-ALIAS: csrr t2, hstateen1h
+# name
+csrrs t1, hstateen1h, zero
+# uimm12
+csrrs t2, 0x61D, zero
+
+# hstateen2h
+# name
+# CHECK-INST: csrrs t1, hstateen2h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x61]
+# CHECK-INST-ALIAS: csrr t1, hstateen2h
+# uimm12
+# CHECK-INST: csrrs t2, hstateen2h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x61]
+# CHECK-INST-ALIAS: csrr t2, hstateen2h
+# name
+csrrs t1, hstateen2h, zero
+# uimm12
+csrrs t2, 0x61E, zero
+
+# hstateen3h
+# name
+# CHECK-INST: csrrs t1, hstateen3h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x61]
+# CHECK-INST-ALIAS: csrr t1, hstateen3h
+# uimm12
+# CHECK-INST: csrrs t2, hstateen3h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x61]
+# CHECK-INST-ALIAS: csrr t2, hstateen3h
+# name
+csrrs t1, hstateen3h, zero
+# uimm12
+csrrs t2, 0x61F, zero

diff  --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 69f9d1f83e6a..7c57ee389af8 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -1015,3 +1015,63 @@ csrrs t2, 0x73E, zero
 csrrs t1, mhpmevent31h, zero
 # uimm12
 csrrs t2, 0x73F, zero
+
+#########################################
+# State Enable Extension (Smstateen)
+#########################################
+
+# mstateen0h
+# name
+# CHECK-INST: csrrs t1, mstateen0h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x31]
+# CHECK-INST-ALIAS: csrr t1, mstateen0h
+# uimm12
+# CHECK-INST: csrrs t2, mstateen0h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x31]
+# CHECK-INST-ALIAS: csrr t2, mstateen0h
+# name
+csrrs t1, mstateen0h, zero
+# uimm12
+csrrs t2, 0x31C, zero
+
+# mstateen1h
+# name
+# CHECK-INST: csrrs t1, mstateen1h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x31]
+# CHECK-INST-ALIAS: csrr t1, mstateen1h
+# uimm12
+# CHECK-INST: csrrs t2, mstateen1h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x31]
+# CHECK-INST-ALIAS: csrr t2, mstateen1h
+# name
+csrrs t1, mstateen1h, zero
+# uimm12
+csrrs t2, 0x31D, zero
+
+# mstateen2h
+# name
+# CHECK-INST: csrrs t1, mstateen2h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x31]
+# CHECK-INST-ALIAS: csrr t1, mstateen2h
+# uimm12
+# CHECK-INST: csrrs t2, mstateen2h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x31]
+# CHECK-INST-ALIAS: csrr t2, mstateen2h
+# name
+csrrs t1, mstateen2h, zero
+# uimm12
+csrrs t2, 0x31E, zero
+
+# mstateen3h
+# name
+# CHECK-INST: csrrs t1, mstateen3h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x31]
+# CHECK-INST-ALIAS: csrr t1, mstateen3h
+# uimm12
+# CHECK-INST: csrrs t2, mstateen3h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x31]
+# CHECK-INST-ALIAS: csrr t2, mstateen3h
+# name
+csrrs t1, mstateen3h, zero
+# uimm12
+csrrs t2, 0x31F, zero

diff  --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index 41f49265c358..69349ab90144 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -118,3 +118,13 @@ csrrs t1, mhpmevent28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system reg
 csrrs t1, mhpmevent29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
 csrrs t1, mhpmevent30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
 csrrs t1, mhpmevent31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, mstateen0h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, hstateen0h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled

diff  --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
index 51be4f568f2e..d62d21428a31 100644
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -245,3 +245,63 @@ csrrs t2, 0x5A8, zero
 csrrs t1, scountovf, zero
 # uimm12
 csrrs t2, 0xDA0, zero
+
+#########################################
+# State Enable Extension (Smstateen)
+#########################################
+
+# sstateen0
+# name
+# CHECK-INST: csrrs t1, sstateen0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x10]
+# CHECK-INST-ALIAS: csrr t1, sstateen0
+# uimm12
+# CHECK-INST: csrrs t2, sstateen0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x10]
+# CHECK-INST-ALIAS: csrr t2, sstateen0
+# name
+csrrs t1, sstateen0, zero
+# uimm12
+csrrs t2, 0x10C, zero
+
+# sstateen1
+# name
+# CHECK-INST: csrrs t1, sstateen1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x10]
+# CHECK-INST-ALIAS: csrr t1, sstateen1
+# uimm12
+# CHECK-INST: csrrs t2, sstateen1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x10]
+# CHECK-INST-ALIAS: csrr t2, sstateen1
+# name
+csrrs t1, sstateen1, zero
+# uimm12
+csrrs t2, 0x10D, zero
+
+# sstateen2
+# name
+# CHECK-INST: csrrs t1, sstateen2, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x10]
+# CHECK-INST-ALIAS: csrr t1, sstateen2
+# uimm12
+# CHECK-INST: csrrs t2, sstateen2, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x10]
+# CHECK-INST-ALIAS: csrr t2, sstateen2
+# name
+csrrs t1, sstateen2, zero
+# uimm12
+csrrs t2, 0x10E, zero
+
+# sstateen3
+# name
+# CHECK-INST: csrrs t1, sstateen3, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x10]
+# CHECK-INST-ALIAS: csrr t1, sstateen3
+# uimm12
+# CHECK-INST: csrrs t2, sstateen3, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x10]
+# CHECK-INST-ALIAS: csrr t2, sstateen3
+# name
+csrrs t1, sstateen3, zero
+# uimm12
+csrrs t2, 0x10F, zero