[llvm] f00a98a - [RISCV] Add CSRs defined in the recently ratified Sscofpmf extension
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 15 00:36:39 PST 2022
Author: Alex Bradbury
Date: 2022-01-15T08:35:13Z
New Revision: f00a98a0a90e80f9790e6b505f5a5d4d64741690
URL: https://github.com/llvm/llvm-project/commit/f00a98a0a90e80f9790e6b505f5a5d4d64741690
DIFF: https://github.com/llvm/llvm-project/commit/f00a98a0a90e80f9790e6b505f5a5d4d64741690.diff
LOG: [RISCV] Add CSRs defined in the recently ratified Sscofpmf extension
The "RISC-V Count Overflow and Mode-Based Filtering Extension" was
ratified at the end of last year though hasn't yet been integrated in
the main specification documents (see
<https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions>).
This commit adds the CSRs defined by this extension in
<https://github.com/riscv/riscv-count-overflow/releases/download/v0.5.2/Sscofpmf.pdf>.
Differential Revision: https://reviews.llvm.org/D117308
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/rv32-machine-csr-names.s
llvm/test/MC/RISCV/rv32-only-csr-names.s
llvm/test/MC/RISCV/supervisor-csr-names.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 2a93036f54e49..2677016dc431e 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -154,6 +154,12 @@ def : SysReg<"satp", 0x180>;
def : SysReg<"scontext", 0x5A8>;
+//===----------------------------------------------------------------------===//
+// Supervisor Count Overflow (defined in Sscofpmf)
+//===----------------------------------------------------------------------===//
+
+def : SysReg<"scountovf", 0xDA0>;
+
//===----------------------------------------------------------------------===//
// Hypervisor Trap Setup
//===----------------------------------------------------------------------===//
@@ -306,6 +312,12 @@ def : SysReg<"mcountinhibit", 0x320>;
foreach i = 3...31 in
def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
+// mhpmevent3h-mhpmevent31h at 0x723-0x73F
+foreach i = 3...31 in {
+ let isRV32Only = 1 in
+ def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
+}
+
//===----------------------------------------------------------------------===//
// Debug/ Trace Registers (shared with Debug Mode)
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 221bd773e0ce2..69f9d1f83e6af 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -605,3 +605,413 @@ csrrs t2, 0xB9E, zero
csrrs t1, mhpmcounter31h, zero
# uimm12
csrrs t2, 0xB9F, zero
+
+######################################
+# Machine Counter Setup
+######################################
+
+# mhpmevent3h
+# name
+# CHECK-INST: csrrs t1, mhpmevent3h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent3h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent3h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent3h
+# name
+csrrs t1, mhpmevent3h, zero
+# uimm12
+csrrs t2, 0x723, zero
+
+# mhpmevent4h
+# name
+# CHECK-INST: csrrs t1, mhpmevent4h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent4h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent4h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent4h
+# name
+csrrs t1, mhpmevent4h, zero
+# uimm12
+csrrs t2, 0x724, zero
+
+# mhpmevent5h
+# name
+# CHECK-INST: csrrs t1, mhpmevent5h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent5h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent5h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent5h
+# name
+csrrs t1, mhpmevent5h, zero
+# uimm12
+csrrs t2, 0x725, zero
+
+# mhpmevent6h
+# name
+# CHECK-INST: csrrs t1, mhpmevent6h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent6h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent6h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent6h
+# name
+csrrs t1, mhpmevent6h, zero
+# uimm12
+csrrs t2, 0x726, zero
+
+# mhpmevent7h
+# name
+# CHECK-INST: csrrs t1, mhpmevent7h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent7h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent7h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent7h
+# name
+csrrs t1, mhpmevent7h, zero
+# uimm12
+csrrs t2, 0x727, zero
+
+# mhpmevent8h
+# name
+# CHECK-INST: csrrs t1, mhpmevent8h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent8h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent8h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent8h
+# name
+csrrs t1, mhpmevent8h, zero
+# uimm12
+csrrs t2, 0x728, zero
+
+# mhpmevent9h
+# name
+# CHECK-INST: csrrs t1, mhpmevent9h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent9h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent9h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent9h
+# name
+csrrs t1, mhpmevent9h, zero
+# uimm12
+csrrs t2, 0x729, zero
+
+# mhpmevent10h
+# name
+# CHECK-INST: csrrs t1, mhpmevent10h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent10h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent10h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent10h
+# name
+csrrs t1, mhpmevent10h, zero
+# uimm12
+csrrs t2, 0x72a, zero
+
+# mhpmevent11h
+# name
+# CHECK-INST: csrrs t1, mhpmevent11h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent11h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent11h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent11h
+# name
+csrrs t1, mhpmevent11h, zero
+# uimm12
+csrrs t2, 0x72B, zero
+
+# mhpmevent12h
+# name
+# CHECK-INST: csrrs t1, mhpmevent12h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent12h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent12h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent12h
+# name
+csrrs t1, mhpmevent12h, zero
+# uimm12
+csrrs t2, 0x72C, zero
+
+# mhpmevent13h
+# name
+# CHECK-INST: csrrs t1, mhpmevent13h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent13h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent13h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent13h
+# name
+csrrs t1, mhpmevent13h, zero
+# uimm12
+csrrs t2, 0x72D, zero
+
+# mhpmevent14h
+# name
+# CHECK-INST: csrrs t1, mhpmevent14h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent14h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent14h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent14h
+# name
+csrrs t1, mhpmevent14h, zero
+# uimm12
+csrrs t2, 0x72E, zero
+
+# mhpmevent15h
+# name
+# CHECK-INST: csrrs t1, mhpmevent15h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x72]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent15h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent15h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x72]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent15h
+# name
+csrrs t1, mhpmevent15h, zero
+# uimm12
+csrrs t2, 0x72F, zero
+
+# mhpmevent16h
+# name
+# CHECK-INST: csrrs t1, mhpmevent16h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent16h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent16h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent16h
+# name
+csrrs t1, mhpmevent16h, zero
+# uimm12
+csrrs t2, 0x730, zero
+
+# mhpmevent17h
+# name
+# CHECK-INST: csrrs t1, mhpmevent17h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent17h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent17h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent17h
+# name
+csrrs t1, mhpmevent17h, zero
+# uimm12
+csrrs t2, 0x731, zero
+
+# mhpmevent18h
+# name
+# CHECK-INST: csrrs t1, mhpmevent18h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent18h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent18h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent18h
+# name
+csrrs t1, mhpmevent18h, zero
+# uimm12
+csrrs t2, 0x732, zero
+
+# mhpmevent19h
+# name
+# CHECK-INST: csrrs t1, mhpmevent19h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent19h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent19h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent19h
+# name
+csrrs t1, mhpmevent19h, zero
+# uimm12
+csrrs t2, 0x733, zero
+
+# mhpmevent20h
+# name
+# CHECK-INST: csrrs t1, mhpmevent20h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent20h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent20h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent20h
+# name
+csrrs t1, mhpmevent20h, zero
+# uimm12
+csrrs t2, 0x734, zero
+
+# mhpmevent21h
+# name
+# CHECK-INST: csrrs t1, mhpmevent21h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent21h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent21h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent21h
+# name
+csrrs t1, mhpmevent21h, zero
+# uimm12
+csrrs t2, 0x735, zero
+
+# mhpmevent22h
+# name
+# CHECK-INST: csrrs t1, mhpmevent22h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent22h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent22h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent22h
+# name
+csrrs t1, mhpmevent22h, zero
+# uimm12
+csrrs t2, 0x736, zero
+
+# mhpmevent23h
+# name
+# CHECK-INST: csrrs t1, mhpmevent23h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent23h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent23h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent23h
+# name
+csrrs t1, mhpmevent23h, zero
+# uimm12
+csrrs t2, 0x737, zero
+
+# mhpmevent24h
+# name
+# CHECK-INST: csrrs t1, mhpmevent24h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent24h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent24h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent24h
+# name
+csrrs t1, mhpmevent24h, zero
+# uimm12
+csrrs t2, 0x738, zero
+
+# mhpmevent25h
+# name
+# CHECK-INST: csrrs t1, mhpmevent25h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent25h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent25h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent25h
+# name
+csrrs t1, mhpmevent25h, zero
+# uimm12
+csrrs t2, 0x739, zero
+
+# mhpmevent26h
+# name
+# CHECK-INST: csrrs t1, mhpmevent26h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent26h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent26h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent26h
+# name
+csrrs t1, mhpmevent26h, zero
+# uimm12
+csrrs t2, 0x73A, zero
+
+# mhpmevent27h
+# name
+# CHECK-INST: csrrs t1, mhpmevent27h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent27h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent27h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent27h
+# name
+csrrs t1, mhpmevent27h, zero
+# uimm12
+csrrs t2, 0x73B, zero
+
+# mhpmevent28h
+# name
+# CHECK-INST: csrrs t1, mhpmevent28h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent28h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent28h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent28h
+# name
+csrrs t1, mhpmevent28h, zero
+# uimm12
+csrrs t2, 0x73C, zero
+
+# mhpmevent29h
+# name
+# CHECK-INST: csrrs t1, mhpmevent29h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent29h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent29h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent29h
+# name
+csrrs t1, mhpmevent29h, zero
+# uimm12
+csrrs t2, 0x73D, zero
+
+# mhpmevent30h
+# name
+# CHECK-INST: csrrs t1, mhpmevent30h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent30h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent30h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent30h
+# name
+csrrs t1, mhpmevent30h, zero
+# uimm12
+csrrs t2, 0x73E, zero
+
+# mhpmevent31h
+# name
+# CHECK-INST: csrrs t1, mhpmevent31h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x73]
+# CHECK-INST-ALIAS: csrr t1, mhpmevent31h
+# uimm12
+# CHECK-INST: csrrs t2, mhpmevent31h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x73]
+# CHECK-INST-ALIAS: csrr t2, mhpmevent31h
+# name
+csrrs t1, mhpmevent31h, zero
+# uimm12
+csrrs t2, 0x73F, zero
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index 50ffe5f9bc91e..41f49265c3585 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -88,3 +88,33 @@ csrrs t1, mhpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system r
csrrs t1, mhpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, mhpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, mhpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, mhpmevent3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent22h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent23h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmevent31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
index 9f8f3007a0b99..51be4f568f2e8 100644
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -227,3 +227,21 @@ csrrs t2, 0x180, zero
csrrs t1, scontext, zero
# uimm12
csrrs t2, 0x5A8, zero
+
+#########################################
+# Supervisor Count Overflow (Sscofpmf)
+#########################################
+
+# scountovf
+# name
+# CHECK-INST: csrrs t1, scountovf, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xda]
+# CHECK-INST-ALIAS: csrr t1, scountovf
+# uimm12
+# CHECK-INST: csrrs t2, scountovf, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xda]
+# CHECK-INST-ALIAS: csrr t2, scountovf
+# name
+csrrs t1, scountovf, zero
+# uimm12
+csrrs t2, 0xDA0, zero
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