[llvm] 0ee679e - [RISCV] Add CSRs defined in the recently ratified Sstc extension
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 15 00:36:42 PST 2022
Author: Alex Bradbury
Date: 2022-01-15T08:36:04Z
New Revision: 0ee679e22cfba9dfd5f6d07e7ff9687192419034
URL: https://github.com/llvm/llvm-project/commit/0ee679e22cfba9dfd5f6d07e7ff9687192419034
DIFF: https://github.com/llvm/llvm-project/commit/0ee679e22cfba9dfd5f6d07e7ff9687192419034.diff
LOG: [RISCV] Add CSRs defined in the recently ratified Sstc extension
The 'RISC-V "stimecmp / vstimecmp" Extension' was ratified at the end of
last year though hasn't yet been integrated in the main specification
documents (see
<https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions>).
RISC-V "stimecmp / vstimecmp" Extension
<https://github.com/riscv/riscv-time-compare/releases/download/v0.5.4/Sstc.pdf>.
Differential Revision: https://reviews.llvm.org/D117311
Added:
llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
Modified:
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/hypervisor-csr-names.s
llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
llvm/test/MC/RISCV/rv32-only-csr-names.s
llvm/test/MC/RISCV/supervisor-csr-names.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 78af112b0291..3a3d5ba732b6 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -125,6 +125,9 @@ def : SysReg<"sideleg", 0x103>;
def : SysReg<"sie", 0x104>;
def : SysReg<"stvec", 0x105>;
def : SysReg<"scounteren", 0x106>;
+def : SysReg<"stimecmp", 0x14D>;
+let isRV32Only = 1 in
+def : SysReg<"stimecmph", 0x15D>;
//===----------------------------------------------------------------------===//
// Supervisor Configuration
@@ -221,6 +224,9 @@ def : SysReg<"vsepc", 0x241>;
def : SysReg<"vscause", 0x242>;
def : SysReg<"vstval", 0x243>;
def : SysReg<"vsip", 0x244>;
+def : SysReg<"vstimecmp", 0x24D>;
+let isRV32Only = 1 in
+def : SysReg<"vstimecmph", 0x25D>;
def : SysReg<"vsatp", 0x280>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/hypervisor-csr-names.s b/llvm/test/MC/RISCV/hypervisor-csr-names.s
index 8f76b3d1450d..00006201de8e 100644
--- a/llvm/test/MC/RISCV/hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/hypervisor-csr-names.s
@@ -360,6 +360,20 @@ csrrs t1, vsip, zero
# uimm12
csrrs t2, 0x244, zero
+# vstimecmp
+# name
+# CHECK-INST: csrrs t1, vstimecmp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x24]
+# CHECK-INST-ALIAS: csrr t1, vstimecmp
+# uimm12
+# CHECK-INST: csrrs t2, vstimecmp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x24]
+# CHECK-INST-ALIAS: csrr t2, vstimecmp
+# name
+csrrs t1, vstimecmp, zero
+# uimm12
+csrrs t2, 0x24D, zero
+
# vsatp
# name
# CHECK-INST: csrrs t1, vsatp, zero
diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index c84553b578c1..f7d2341070ac 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -40,6 +40,24 @@ csrrs t1, htimedeltah, zero
# uimm12
csrrs t2, 0x615, zero
+################################
+# Virtual Supervisor Registers
+################################
+
+# vstimecmph
+# name
+# CHECK-INST: csrrs t1, vstimecmph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x25]
+# CHECK-INST-ALIAS: csrr t1, vstimecmph
+# uimm12
+# CHECK-INST: csrrs t2, vstimecmph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x25]
+# CHECK-INST-ALIAS: csrr t2, vstimecmph
+# name
+csrrs t1, vstimecmph, zero
+# uimm12
+csrrs t2, 0x25D, zero
+
#########################################
# State Enable Extension (Smstateen)
#########################################
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index 69349ab90144..10c4b9cc6750 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -128,3 +128,6 @@ csrrs t1, hstateen0h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system regis
csrrs t1, hstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, stimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, vstimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
diff --git a/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
new file mode 100644
index 000000000000..28dcd19bd38b
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
@@ -0,0 +1,23 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN: | llvm-objdump -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Supervisor Trap Setup
+##################################
+
+# stimecmph
+# name
+# CHECK-INST: csrrs t1, stimecmph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x15]
+# CHECK-INST-ALIAS: csrr t1, stimecmph
+# uimm12
+# CHECK-INST: csrrs t2, stimecmph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x15]
+# CHECK-INST-ALIAS: csrr t2, stimecmph
+# name
+csrrs t1, stimecmph, zero
+# uimm12
+csrrs t2, 0x15D, zero
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
index d62d21428a31..e2bf942beac0 100644
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -98,6 +98,20 @@ csrrs t1, scounteren, zero
# uimm12
csrrs t2, 0x106, zero
+# stimecmp
+# name
+# CHECK-INST: csrrs t1, stimecmp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x14]
+# CHECK-INST-ALIAS: csrr t1, stimecmp
+# uimm12
+# CHECK-INST: csrrs t2, stimecmp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x14]
+# CHECK-INST-ALIAS: csrr t2, stimecmp
+# name
+csrrs t1, stimecmp, zero
+# uimm12
+csrrs t2, 0x14D, zero
+
##################################
# Supervisor Configuration
##################################
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