[PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.

Jessica Clarke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 14 04:18:49 PST 2022

Previous message: [PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.
Next message: [PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

jrtc27 accepted this revision.
jrtc27 added a comment.
This revision is now accepted and ready to land.

Ouch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117279/new/

https://reviews.llvm.org/D117279

Previous message: [PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.
Next message: [PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list