[PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGac6b4896ea91: [RISCV] Honor the VT when converting float point register names to register… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117279/new/

https://reviews.llvm.org/D117279

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

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