[PATCH] D117279: [RISCV] Honor the VT when converting float point register names to register class for inline assembly.

[Craig Topper via Phabricator via llvm-commits]

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It appears the code here was written for the inline asm clobbering
a specific register, but it also gets used for named input and
output registers.

For the input and output case, we should honor the VT so we
don't insert conversion instructions around the inline assembly.

For the clobber, case we need to pick the largest register class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117279

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

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