[PATCH] D116019: [RISCV][NFC] Use foreach to refactor vector load/store whole register instructions' definition.

Jianjian Guan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 5 23:48:35 PST 2022

Previous message: [PATCH] D116724: [RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.
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jacquesguan added a comment.

ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116019/new/

https://reviews.llvm.org/D116019

Previous message: [PATCH] D116724: [RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.
Next message: [PATCH] D116019: [RISCV][NFC] Use foreach to refactor vector load/store whole register instructions' definition.
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