[PATCH] D116310: [RISCV] Support passing scalable vectur values through the stack.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 396306.
HsiangKai added a comment.

Update the test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116310/new/

https://reviews.llvm.org/D116310

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
  llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll

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