[PATCH] D115881: [WIP][AMDGPU][GlobalISel] Add patterns for no-return atomic ops with single address and data in tblgen.

[Abinav Puthan Purayil via Phabricator via llvm-commits]

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SelectionDAG relies on MachineInstr's HasPostISelHook for selecting the
no-return atomic ops.  This changes partially achieves the same in tblgen.
Since global-isel, at the moment, doesn't handle HasPostISelHook, this will
enable the no-return atomic ops selection in global-isel.

Even though this change can't enable us to eliminate HasPostISelHook handling,
it should, hopefully, point us in that direction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115881

Files:
  llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmin.ll
  llvm/test/CodeGen/AMDGPU/lds-atomic-fadd.ll
  llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
  llvm/test/CodeGen/AMDGPU/local-atomics-fp.ll

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