[PATCH] D115863: [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

This is likely to be an improvement, because we can calculate the predicate (ptrue+rev) before the loop, at which point all we need is the splice inside the loop, whereas currently it requires both a lastb + insr inside the loop.
Just left a few nits, otherwise looks good to me.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7797
+  // number of elements.
+  if (Ty.isScalableVector() && IdxVal >= -8 && IdxVal <= -1 &&
+      -IdxVal <= Ty.getVectorMinNumElements()) {
----------------
nit: `IdxVal < 0 && abs(IdxVal) <= 8`


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7798
+  if (Ty.isScalableVector() && IdxVal >= -8 && IdxVal <= -1 &&
+      -IdxVal <= Ty.getVectorMinNumElements()) {
+    SDLoc DL(Op);
----------------
I don't think this check is necessary?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7803
+    EVT PredVT = Ty.changeVectorElementType(MVT::i1);
+    SDValue Pred = getPTrue(DAG, DL, PredVT, -IdxVal);
+    Pred = DAG.getNode(ISD::VECTOR_REVERSE, DL, PredVT, Pred);
----------------
nit: can you use abs(IdxVal) instead? (I personally find that slightly more readable)


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  https://reviews.llvm.org/D115863/new/

https://reviews.llvm.org/D115863