[PATCH] D115863: [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE

[David Sherwood via Phabricator via llvm-commits]

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For certain negative indices passed to the VECTOR_SPLICE operation
we can actually directly use the SVE splice instruction by creating
the appropriate predicate. The predicate needs to be constructed in
such a way that all but the last -idx elements are false. We can do
this efficiently using a combination of 'ptrue' (with the appropriate
fixed pattern, e.g. vl1, vl2, etc.) and 'rev'. The advantage of using
these instructions to generate the predicate is they do not set any
flags, unlike the whilelo instruction. This is critical when the splice
operation is in a loop, since we want MachineLICM to hoist the
predicate generation out of the loop.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115863

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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