[PATCH] D115863: [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7798
+  if (Ty.isScalableVector() && IdxVal >= -8 && IdxVal <= -1 &&
+      -IdxVal <= Ty.getVectorMinNumElements()) {
+    SDLoc DL(Op);
----------------
sdesmalen wrote:
> I don't think this check is necessary?
Unforunately, it is necessary for correctness because the ptrue behaviour changes completely when you specify a fixed pattern that exceeds the number of elements. For example, if we do something like this:

  ptrue p0.d, vl4

and your vector length=128 bits, then ptrue actually returns an all-false predicate! So the maximum we can do safely without knowing vscale is:

  ptrue p0.d, vl2


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115863/new/

https://reviews.llvm.org/D115863