[PATCH] D115720: [RISCV] Fix whole vector register move instruction's vector register constraint.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 15 12:26:44 PST 2021

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craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D115720/new/

https://reviews.llvm.org/D115720

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