[PATCH] D115720: [RISCV] Fix whole vector register move instruction's vector register constraint.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan created this revision.
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According to the v-spec, the source and destination VR of vmv<nr>r.v should be aligned for the VR group size.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115720

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/invalid.s

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