[PATCH] D115720: [RISCV] Fix whole vector register move instruction's vector register constraint.

[Jianjian Guan via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd3c2ad154ec8: [RISCV] Fix whole vector register move instruction's vector register constraint. (authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115720/new/

https://reviews.llvm.org/D115720

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/invalid.s

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