[PATCH] D115133: [RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1577
+  // vsetivli rd, uimm, 0xabc or vsetvli rd, rs1, 0xabc
+  if (getLexer().is(AsmToken::Integer)) {
+    int64_t Val = getLexer().getTok().getIntVal();
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craig.topper wrote:
> Does binutils only except literal integers or does it support expressions?
I have tested the newest master of binutils,

1. it does not support vtype being an expression, in fact there is no expression  cases in binutils's unit tests.

2. it still generate wrong dissambly against illegal vtype, for example, larger types such as `e128`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115133/new/

https://reviews.llvm.org/D115133