[PATCH] D115133: [RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1577
+  // vsetivli rd, uimm, 0xabc or vsetvli rd, rs1, 0xabc
+  if (getLexer().is(AsmToken::Integer)) {
+    int64_t Val = getLexer().getTok().getIntVal();
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Does binutils only except literal integers or does it support expressions?


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1581
+    getLexer().Lex();
+    // illegal values: vlmul[2:0]=4, vsew[2:0]=0b1xx, non-zero bits 8/9/10.
+    if (RISCVVType::getVLMUL(Val) == RISCVII::VLMUL::LMUL_RESERVED ||
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There are no illegal values in the immediate form for vlmul or vsew. The intention was to allow the disassembler to print immediates for reserved encodings. Anything that the disassembler prints must be parseable.

We do need to make sure the immedaite fits in 11 bits for vsetvli and 10 bits for vsetivli.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115133/new/

https://reviews.llvm.org/D115133